As a semiconductor device becomes highly integrated, distances between wiring patterns included in the semiconductor device decrease. Thus, a parasitic capacitance between the neighboring wiring patterns may increase, which may reduce the reliability of the semiconductor device.
Additionally, a low-k insulation layer adjacent to the wiring patterns may be damaged while performing, for example, an etching process or a thermal treatment for the formation of the wiring patterns, and thus the parasitic capacitance may be further increased by the damage to the low-k insulation layer.